1. Field of the Invention
The present invention relates to dynamic logic and register functions, and more particularly to a dynamic logic register that provides registered outputs for logic evaluation functions, where the hold time of the register is dependent on the state of the input data to the register.
2. Description of the Related Art
Integrated circuits use a remarkable number of registers, particularly those having a synchronous pipeline architecture. Register logic is employed to hold the outputs of devices and circuits for a period of time so that these outputs can be received by other devices and circuits. In a clocked system, such as a pipeline microprocessor, registers are used to latch and hold the outputs of a given pipeline stage for a period of one clock cycle so that input circuits in a subsequent stage can receive the outputs during that period while the given pipeline stage is concurrently generating new outputs.
In the past, it has been common practice to precede and follow complex logical evaluation circuits, such as multiple-input multiplexers (muxes), multi-bit encoders, etc., with registers to hold the inputs to and the outputs from the evaluation circuits. Generally, these registers have associated setup and hold time requirements, both of which constrain the evaluation circuits in the preceding stage. In addition, registers have corresponding clock-to-output time characteristics, which constrain the evaluation circuits in subsequent stages. The “speed” of a register is typically judged in terms of its data-to-output time, that is, the sum of its setup time and clock-to-output time.
Preceding and following a logical evaluation circuit with traditional register circuits introduces delays into a pipeline system whose cumulative effect results in significantly slower operating speeds. More specifically, one notable source of these delays is the setup time requirements that must be satisfied by logical evaluation circuits in order to ensure stable registered outputs. It is desired to reduce these delays to provide additional time in each stage and to thereby increase overall speed of the pipeline system. Techniques used to reduce the setup and clock-to-output delays (e.g., domino-type configurations) often introduce increased hold time requirements. In particular, when a data input is clocked into these register circuits, the state of the data input must be held constant for a specified period of time (i.e., the “hold” time) before it can change. If it changes before the hold time expires, then an incorrect registered output possible.
Many devices, to include conventional domino-type circuits, exhibit a hold time requirement that is approximately the width of a corresponding clock pulse. Consequently, to reduce the hold time requirement for a conventional domino circuit, many designers employ a pulsed clock signal, that is, a clock signal whose “clocking” state is significantly short in duration as compared to its non-clocking state. It is not uncommon today to find pulsed clock signals having less than 10 percent duty cycles for their corresponding clocking states.
Accordingly, it is also desired to provide a registered evaluation circuit apparatus and methods which exhibit markedly reduced hold time requirements, and which moreover exhibit hold time requirements that are not dependent upon providing a corresponding pulsed clock signal.